Microdevices, such as integrated microcircuits and microelectromechanical systems (MEMS), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microdevices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microdevice fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows for integrated microcircuits. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that can be performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). As part of the creation of a logical design, a designer will also implement a place-and-route process to determine the placement of the various portions of the circuit, along with an initial routing of interconnections between those portions. The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices, such as transistors, resistors, and capacitors, which will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design can be again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components, e.g., contacts, gates, etc., and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Once the groups of geometric elements representing circuit device components have been placed, geometric elements representing connection lines then are then placed between these geometric elements according to the predetermined route. These lines will form the wiring used to interconnect the electronic devices.
Typically, a designer will perform a number of analyses on the resulting layout design data. For example, with integrated circuits, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships as described in the device design. The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements. Still further, the layout design may be modified to include the use of redundant geometric elements or the addition of corrective features to various geometric elements, to counteract limitations in the manufacturing process, etc. For example, the design flow process may include one or more resolution enhancement technique (RET) processes, that modify the layout design data to improve the usable resolution of the reticle or mask created from the design in a photolithographic manufacturing process.
After the layout design has been finalized, it is converted into a format that can be employed by a mask or reticle writing tool to create a mask or reticle for use in a photolithographic manufacturing process. The written masks or reticles then can be used in a photolithographic process to expose selected areas of a wafer to light or other radiation in order to produce the desired integrated microdevice structures on the wafer.
Returning to “functional verification,” this type of analysis begins with a circuit design coded at a register transfer level (RTL), which can be simulated by a design verification tool. A designer, for example, utilizing the design verification tool, can generate a test bench that, when input to the simulated circuit design, can allow the design verification tool to analyze or verify the functionality of the simulated circuit design. Due to the complexity in many circuit designs, it is often impractical to perform functional verification utilizing test benches that cover every possible input vector for the simulated circuit design. Thus, many designers generate test benches having just a subset of the possible input vectors.
The design verification tool can quantify how well a test bench came to covering or adequately exercising the simulated circuit design, for example, with various coverage metrics. For example, the design verification tool can use a statement coverage metric to quantify whether each executable statement or line of code in the simulated circuit design was executed in response to the test bench. The design verification tool can use a decision coverage metric to quantify whether each coded decision path was utilized in response to the test bench. The design verification tool can use a condition coverage metric to quantify whether all outcomes of a condition, for example, both true and false, were realized in response to the test bench. The design verification tool can use an expression coverage metric to quantify whether expressions in the code of the circuit design, such as Boolean logic structures, were adequately exercised or functionally verified in response to the test bench. The design verification tool can, of course, incorporate many different coverage metrics, other than those discussed above.
In some cases, the design verification tool can cover an expression when the expression receives fewer than all of the possible input vectors defined by its available inputs. For example, the design verification tool can deem a two-input expression (A or B) completely covered when the expression receives three, (A,B)=(0,0), (0,1), and (1,0), of the four possible input vectors, (A,B)=(0,0), (0,1), (1,0), and (1,1), in response to a test bench, as the reception of input vectors (A,B)=(0,1) and (1,0) renders input vector (A,B)=(1,1) superfluous. To determine which of the possible input vectors may be excluded and still allow for complete coverage of each expression in the circuit design, conventionally the design verification tool generates truth-tables including all of the possible input vectors for each expression, and then selectively trims input vectors from the truth-tables in order to generate lists of input vectors that, if received, would completely cover each of the expressions. The design verification tool can utilize these lists of input vectors during simulation of the circuit design to identify whether the test bench includes adequate stimuli to completely cover each expression.
While analyzing the circuit design before simulation can identify truncated lists of input vectors that can completely cover each expression, the number of input vectors initially generated in the truth-tables varies exponentially (2N) based on the number of inputs (N) in each expression. Many design verification tools endure long processing times and large memory requirements in order to initially generate these truth-tables and identify and store the truncated lists of input vectors for each expression in the circuit design.